`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:01:55 05/04/2013 
// Design Name: 
// Module Name:    InstructionDecoder 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module InstructionDecoder(
    input pop_data,
   input [(2 * N) - 1: 0] data_in,
    output [N - 1 : 0] data_out,
    output [1 : 0] addr_out,
    output reg ldr,
	 output reg sum,
	 output reg cmp,
	 output reg mul,
	 output reg write_to_reg
    );
	 
	 parameter N = 4;
	 
	 always @ * begin
		if (pop_data && data_in[1 : 0] == 2'b00) begin
			ldr = 1'b1;
			sum = 1'b0;
			mul = 1'b0;
			cmp = 1'b0;
		end
		else if (pop_data && data_in[1 : 0] == 2'b01) begin
			ldr = 1'b0;
			sum = 1'b1;
			mul = 1'b0;
			cmp = 1'b0;
			write_to_reg = 1'b1;
		end
		else if (pop_data && data_in[1 : 0] == 2'b10) begin
			ldr = 1'b0;
			sum = 1'b0;
			mul = 1'b1;
			cmp = 1'b0;
			write_to_reg = 1'b1;
		end
		else if (pop_data && data_in[1 : 0] == 2'b11) begin
			ldr = 1'b0;
			sum = 1'b0;
			mul = 1'b0;
			cmp = 1'b1;
			write_to_reg = 1'b1;
		end
		else begin
			ldr = 1'b0;
			sum = 1'b0;
			mul = 1'b0;
			cmp = 1'b0;
			write_to_reg = 1'b0;
		end
	 end
	 
	 assign addr_out = data_in[3 : 2];
	 assign data_out = data_in[7 : 4];

endmodule
